AI chip outlook: What 35+ semiconductor experts are watching

Qualitate interviewed 35+ experts across two studies covering AI silicon design & sourcing and semiconductor fab equipment & materials. Their firsthand observations offer a closer look at the constraints, spending decisions, and capacity shifts shaping the AI chip market.

Explore selected expert perspectives below and download a 22-page preview of our semiconductor research.

Will more packaging capacity solve the AI chip supply problem?

A hyperscaler architect expects the bottleneck to shift toward memory as packaging capacity expands.

“My simple view is the market is expecting packaging relief to solve the supply problem, but the constraint moves from packaging towards the memory instead. We're just moving the constraint to the memory.”

HPC Firmware Architect, Hyperscaler with custom silicon

What does rising semiconductor capex really tell us about AI demand?

One cost analyst argues that higher memory prices can obscure the underlying spending picture.

“The current craziness of the CapEx guidance is mostly driven by the crazy memory price... What investors should look for is the actual spend minus that memory surcharge. If that number decreases, then it would tell you that AI demand may not be concrete.”

Supply Chain Cost Analyst, Hyperscaler custom-silicon team

Which semiconductor supply risks sit below the headline names?

A device engineering director points to specialized suppliers whose capacity can constrain the entire production chain.

“There are suppliers down the chain like Carl Zeiss, for example, who makes those fancy mirrors and lenses for EUV... one supplier, no diversification, no substitute, and extremely long cycle times. And nobody is talking about them scaling capacity.”

Director, Leading-Edge Device Engineering, Integrated device manufacturer (IDM)

Where is the market underestimating semiconductor supply constraints?

An engineer working in DRAM manufacturing sees a gap between the attention paid to front-end fabrication and the constraints further downstream.

“The biggest gap is that the Street overestimates front-end EUV or photo constraints and underestimates back-end constraints in advanced packaging, test, or substrates.”

Application Engineer, High-volume DRAM fab

What does demand look like on the fab floor?

At one semiconductor foundry, a process engineer describes production already committed to customers.

“Every wafer that we start has been purchased.”

Senior Process Engineer, Semiconductor foundry

Explore the research behind the quotes

Download a 22-page preview of Qualitate’s semiconductor research for selected findings from our expert interviews.

For the full interview transcripts and executive briefings, connect with our team. Compare expert perspectives and dig into the companies, technologies and purchasing decisions that matter to your research.